What is the correct bits definition of the power management signals pm_state_o[2:0] when using the Intel® FPGA P-Tile Avalon® Streaming IP for PCIe Express*?

Description

The pm_state_o[2:0] signals indicate the current power state of the Intel® FPGA P-Tile Avalon® Streaming IP for PCIe Express*

The correct definition is shown below:

3’b000 = L0 or IDLE

3’b001 = L0s

3’b010 = L1

3’b011 = L2

3’b100 = L3

This information was incorrect in 2020.12.14 and earlier version of the user guide.

Resolution

This information has been included in the 2021.02.18 version of the Intel® FPGA P-Tile Avalon® Streaming IP for PCIe Express* user guide documentation