What does the per lane information seen in the P-Tile Debug Toolkit tab correspond to ?

Description

You can see the per-lane information under each tab in the P-Tile Debug Toolkit.

• In the Configuration Space tab, there is the logical lanes information for each port
• In the Channels Parameter tab, there is the physical lanes information for each port

•  In the Eye Viewer Controls tab, there is the physical lanes information for each port

Resolution

This information is added to the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express User Guide starting with v21.4 onwards.