What could be the reason for DRC warning on false paths when expressed as multicycle assignments in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP ?

Description

In Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP, DRC warning is expected when expressed as multicycle assignments. This constrains the fitter so that it will not use arbitrarily complex routes for these signals.

Resolution

In Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP, the fix to the DRC warnings is to only enable the multicycle paths in the fitter phase. This has no functional effect.  This issue has been fixed in the Intel® Quartus® Prime Pro Edition Software v22.2 and later versions.