What clock should I use to capture the PIPE interface signals on the test_out bus when using SignalTap II Logic Analyzer?

Description

Use pld8gtxclkout to capture the PIPE signals on the test_out interface using the SignalTap™ II Logic Analyzer.  This clock signal is located in the following hierarchy: 

For Arria® V device families: *xcvr_native|inst_av_pcs|inst_av_pcs_ch*
For Stratix® V device families: *xcvr_native|inst_sv_pcs|int_sv_pcs_ch*