What are the recommended requirements for series or parallel termination and signal trace length information for clock and data signal in AN543: Debugging Nios II Software using the Lauterbach ?

Description

There is missing information in AN543: Debugging Nios II Software using the Lauterbach regarding what are the recommended requirements for series or parallel termination and signal trace length information for clock and data signal.

Resolution

To work around this problem, Altera® use the Thevenin termination against VTREF/2 for all signals (clock and signals) on the Pre-Processor. Hence, removing the series termination on the clock (replacing with 0 ohm resistor) will improve the signal integrity.

Besides that, the signal trace requirement is dependent on the exact PCB trace characteristic. It is necessary to limit the skew of the data signals relative to the clock signal.