What are the AXI transaction master IDs (12 bits) on the HPS2FPGA bridge?

Description

The AXI transaction master ID (12 bits) mappings on the HPS2FPGA bridge are documented below:
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Master Name --- ID
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L2M0 (MPU) --- 12'b0xxxxxxxx010
DMA --- 12'b00000xxxx001
EMAC0 --- 12'b10000xxxx001
EMAC1 --- 12'b10000xxxx010
USB0 --- 12'b100000000011
USB1 --- 12'b100000000110
NAND --- 12'b1xxxxxxxx100
ETR --- 12'b100000000000
DAP --- 12'b000000000100
SDMMC --- 12'b100000000101
-----------------------------

Resolution

This information will be added to the next release of the Cyclone® V Device Handbook.