Warning(16735): Verilog HDL warning at ddrx_ropt_ctrl.sv(1821): actual bit length 2 differs from formal bit length 8 for port

Description

This warning might be seen in the Intel® Quartus® Prime Pro Edition Software version 23.3 when you compile a design containing the Memory Subsystem Intel® FPGA IP that instantiates a Content-Addressable Memory Intel® FPGA IP using the MBL algorithm.

Resolution

It is safe to ignore this warning.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.