Warning(13228): Verilog HDL or VHDL warning at altera_remote_update_core.sv(292): latch inferred for net next_state[31]

Description

Due to a problem in the Intel® Quartus® Prime Standard Edition software version 17.1 Update 2, you may observe the following warning messages when migrating a design that includes the Remote Update Intel® FPGA IP Core to the Intel® Quartus® Prime Pro Edition software version 17.1 Update 2:

Warning(13228): Verilog HDL or VHDL warning at altera_remote_update_core.sv(292): latch inferred for net next_state[31]

Warning(16750): Verilog HDL warning at altera_remote_update_core.sv(292): "next_state" inside always_comb block does not represent combinational logic

Warning(13228): Verilog HDL or VHDL warning at altera_remote_update_core.sv(337): latch inferred for net shift_in_counter_en

Warning(16750): Verilog HDL warning at altera_remote_update_core.sv(337): "shift_in_counter_en" inside always_comb block does not represent combinational logic

Resolution

These warnings messages can be safely ignored, no physical latches will be included in the compilation results. To remove the warning messages, please remove the Remote Update Intel® FPGA IP Core related files from your project and create a new instance generated by the Intel® Quartus® Prime Pro edition software.

This problem has been fixed in the Intel® Quartus® Prime Pro Edition software version 18.1.