Warning(13228): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(647): latch inferred for net byteen_array[0][3]

Description

In the Quartus® Prime Standard Edition Software version 17.1 Update 2 and earlier, you may observe a similar warning message when compiling a design that includes a Platform Designer system (.qsys).

Resolution

This warning message can be safely ignored, no physical latches will be included in the compilation results.

This warning will be removed in a future release of the Quartus® Prime Standard Edition Software.