Warning (332060): Node: *altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg was determined to be a clock but was found without an associated clock assignment.

Description

You might see this warning during timing analysis in the Intel® Quartus® Prime Standard Edition Software version 16.0 Update 2 and earlier. The warning occurs  when compiling an Intel® MAX®10 FPGA design containing the altera_onchip_flash component.

Resolution

Apply the following constraints to your Synopsys Design Constraint (.sdc) file manually to work around this problem:

create_generated_clock -name flash_se_neg_reg -divide_by 2 -source [get_pins -compatibility_mode { *altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] [get_pins -compatibility_mode { *altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]