Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

Description

You may see the above warning message when you compile the generated example design of the UniPHY-based DDR3 memory controller.

Resolution

This warning will show up when users don't specify whether they are willing to have feedback and output paths differently.  

Intel® Quartus® will try to match both paths with the same compensation path.  

 

This warning can be fixed by setting the following QSF assignment:

set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK OFF -to *