Warning (16817): Verilog HDL waring at alt_etipc3_nphy_elane.v (12698)

Description

You may see the warning shown above due to module collision when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP.

When multiple instances of the E-tile Hard IP for Ethernet Intel® FPGA IP are used with different configurations within the same Intel® Quartus® Prime project, the design can compile incorrectly and cause fitter errors.

Users will see compilation warnings where settings for modules with the same name are overwritten in Intel® Quartus® Prime compilation and during simulation compilation.

Resolution

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.