Warning (14320): Synthesized away node "<node name>:ALTLVDS_RX_component||fast_clock"

Description

You may see this warning when compiling a VHDL variation file using the ALTLVDS_RX megafunction in the Quartus® II software version 10.0 SP1 and implementing the SERDES in LE mode. Depending on your selections in the ALTLVDS_RX MegaWizard™ Plug-In Manager, the rx_outclock port may be declared as STD_LOGIC_VECTOR (0 DOWNTO 0) instead of simply STD_LOGIC.

This problem may be triggered if you toggle the What is the clock resource used for 'rx_outclock'? setting.

To work around this problem, edit the ALTLVDS_RX variation file. There are four locations that need to be edited:

• In the ENTITY PORT section, replace the text OUT STD_LOGIC_VECTOR (0 DOWNTO 0) with the text OUT STD_LOGIC.
• In the COMPONENT PORT section, replace the text OUT STD_LOGIC_VECTOR (0 DOWNTO 0) with the text OUT STD_LOGIC.
• Under BEGIN, locate the sub_wire that maps the signal to rx_outclock and remove the text (0 DOWNTO 0).
• In the ARCHITECTURE section before the COMPONENT, locate the sub_wire used in the previous step and replace the text STD_LOGIC_VECTOR (0 DOWNTO 0) with the text STD_LOGIC.

This problem is scheduled to be fixed in a future version of the Quartus II software.

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• Error: Port pll_areset is being set to the state USED which is incompatible with the current settings of DESERIALIZATION_FACTOR(<J>), USE_EXTERNAL_PLL(ON). The legal state is UNUSED
• Warning (12010): Port rx_fifo_reset on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be driven by GND.
• Warning (12010): Port rx_dpll_hold on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be driven by GND.
• Warning (12030): Port rx_cda_max on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be left dangling without any fan-out logic.
• Warning (12030): Port rx_dpa_lock_reset on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be driven by GND.
• Warning (12010): Port rx_dpa_locked on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be left dangling without any fan-out logic.
• Warning (12010): Port rx_cda_reset on the entity instantiation of ALTLVDS_RX_component is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be driven by GND.
• How do I keep the setting for the ALTLVDS_RX megafunction when using the MegaWizard Plug-In Manager?