VHDL simulation support is not available when using the High Bandwidth Memory (HBM2E) Interface IP

Description

VHDL support is unavailable for simulating HBM2E designs in Quartus® Prime Pro Edition Software version 22.3 or later.

 

 

Resolution

 To work around this issue:

• Use Verilog format for simulations.
• Create a top-level VHDL wrapper that instantiates the top-level Verilog as a component.

Additional Information

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Software