VHDL-Generated Fileset Can Encounter Synthesis Problems for UniPHY External Memory Interfaces

Description

An error in the VHDL-generated wrapper for the synthesis fileset can result in a variety of synthesis problems.

Resolution

The workaround for this issue is to open the generated wrapper file in a text editor, and replace all ports of the form std_logic_vector(0 downto 0) with std_logic .