VHDL error "Error: Unknown formal identifier pll_slf_rst" and Verilog error "Error: Unresolved defparam reference to pll_slf_rst" generated when simulating ACDS 13.1 update 3 designs

Description

After installing the Altera® Complete Design Suite version 13.1 update 3, you might see an error message when simulating designs targeting Arria® V, Cyclone® V, or Stratix® V devices with Altera PLL IP with the Mentor Graphics® ModelSim®-Altera software. The error message for VHDL users is:

Error: Unknown formal identifier “pll_slf_rst”

The error message for Verilog users is:

Error: Unresolved defparam reference to “pll_slf_rst”

Resolution

This issue has been fixed in the Quartus® II software release version 14.0.

To eliminate the error in the Quartus II software release version 13.1 update 3, compile the following files into a local library directory, and map the libraries altera_lnsim and altera_lnsim_ver to the local library directory:

• quartus\eda\sim_lib\altera_lnsim.sv
• quartus\eda\sim_lib\altera_lnsim_components.vhd (VHDL only)