Verilog HDL error at template_file_name.v(46): zero or negative value for size

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 23.2. You will see the error message seen below when using the M18x19_systolic with Preadder and Coefficient Verilog HDL. Language template.

Verilog HDL error at <template file name>.v(46): zero or negative value for size

Resolution

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.2, follow the steps below: 

Modify the RTL in the Intel® Quartus® Prime Pro Language template  - DSP Features for 20-nm Device - M18x19_systolic with Preadder and Coefficient: 

From:

reg signed [COEF_WIDTH-1:0] c4_coef [0];

To:

reg signed [COEF_WIDTH-1:0] c4_coef[0:0]; 

Or:

reg signed [COEF_WIDTH-1:0] c4_coef; 

This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition Software version 23.3.