Update BFM instance names for some peripherals in HPS Qsys systems

Description

If you generate a hard processor system (HPS) IP in Qsys that contains a NAND Flash Controller, a queued serial peripheral interface (QSPI) Flash Controller or a serial peripheral interface (SPI) Controller, compilation of the Verilog simulation model generated by Qsys might fail.

Resolution

Update the following bus functional model (BFM) sub-component instantiation names in component <Qsys design name>_<HPS IP instance name>_fpga_interfaces:

• Change nand to nand_inst
• Change qspi_sclk_out to qspi_sclk_out_inst
• Change spim0_sclk_out to spim0_sclk_out_inst
• Change spim1_sclk_out to spim1_sclk_out_inst