Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP Cores Fails for Stratix V if You Use ModelSim With Mixed Languages

Description

Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP cores for Stratix V devices fails if you use ModelSim with mixed languages.

Resolution

Turn off ModelSim optimization with the -novpt option of the vsim command..