Simulation Fails for Stratix V Designs Generated Using SOPC Builder

Description

Simulation fails when you use the SOPC builder to generate Verilog HDL or VHDL simulation models for designs targeting Stratix V devices.

This issue affects all Triple-Speed Ethernet designs targeting Stratix V devices.

Resolution

No workaround.

This issue will be fixed in a future version of the Triple Speed Ethernet MegaCore function.