SDRAM ECC Disabled in Preloader

Description

Qsys cannot generate a DDR interface in the HPS component with ECC enabled. If you try to specify such an interface, the result is an interface with no ECC. Depending on the interface width specified, the resulting interface width is as follows:

Specified width	Resulting width
24	16
40	32

Resolution

Upgrade to the Altera Complete Design Suite v13.0 SP1 or later.