RTL Simulation Reports Errors When Using Verilog HDL

Description

EDA RTL simulation started from the Quartus II software reports errors in the ModelSim^® simulator for designs containing Video and Image Processing Suite MegaCore functions when the output files are in Verilog HDL.

This issue affects configurations that use NativeLink to run a ModelSim simulation from Verilog HDL.

An error message reports that software cannot find the Altera library.

Resolution

Compile the file db/alt_cusp90_package.vhd to the Altera library. To perform this compilation, modify the top-level .do script in the simulation/modelsim directory.

This issue will be fixed in a future version of the Video and Image Processing Suite.