RapidIO IP Core VHDL Customer Testbench Fails Simulation For Some Arria V Variations

Description

The VHDL testbench for a RapidIO MegaCore function x1 5.00 Gbaud variation that targets an Arria V device cannot simulate. The reason is that the VHDL port rx_errdetect has the wrong width.

Resolution

To avoid this issue, after you generate your RapidIO MegaCore function instance, perform the following steps:

1. Open the generated file <my_rapidio_ip_core>_hookup.iv in a text editor.
2. Modify the widths as shown in the following two VHDL signal declarations:

wire [3:0] rx_errdetect

wire [3:0] sister_rx_errdetect

3. Save and close the file.

Your testbench can now simulate successfully.

Refer also to RapidIO IP Core Verilog HDL Customer Testbench Fails Simulation For Some Arria V Variations With Mismatched Reference Clock Frequency.

This issue is fixed in version 12.0 of the RapidIO MegaCore function.