RapidIO II MegaCore Function User Guide Does Not Explain sys_clk and Transceiver Reference Clock Constraints

Description

The two RapidIO II IP core input clocks, sys_clk and tx_pll_refclk, must derive from a common clock source. If your design does not enforce this constraint, the IP core may experience FIFO underflow or overflow. However, the RapidIO II MegaCore Function User Guide does not document this constraint.

Resolution

To avoid this issue, ensure that your Avalon system clock, sys_clk, and TX PLL reference clock, tx_pll_refclk, derive from a common clock source.

This issue is fixed in version 14.0 of the RapidIO II MegaCore Function User Guide.