No fPLL Calibration for HDMI Arria 10 Design Example

Description

The Arria 10 design example for the HDMI IP core by default uses fractional phase-locked loop (fPLL) as the transmitter PLL for the transceiver PHY. The fPLL supports reconfiguration, but the recalibration process is targeted for ATX PLL. Reconfiguring your design without recalibrating may impact the robustness of the hardware.

Resolution

To work around this issue, edit the xcvr_gpll_rcfg.c file in software/tx_control_src/ directory before you execute runall.tcl.

Edit the following line in the xcvr_gpll_rcfg.c file:

XCVR_RCFG_WRITE (0x100, 0x00000001); // ATX PLL recalibration

to:

XCVR_RCFG_WRITE (0x100, 0x00000002); // FPLL recalibration

This issue is fixed in version 15.1 Update 1 of the HDMI IP core.