ncelab: *E,CFEPLM : Foreign module port * of mode in must be associated with port/signal of entity/component ALTPCIE_AV_HIP_AST_HWTCL

Description

You may see this error in elaboration process of ncsim simulation with PCIe VHDL simulation code for Arria V Hard IP due to Quartus II software problem.

To prevent this error, you should generate Arria V PCIe simulation model in Verilog language format instead of VHDL format.

This issue is scheduled to be fixed in a future release of Quartus II software.