Mismatched VHDL generic and local parameter types in NC-Sim for Stratix V fractional PLL simulation models

Description

If you use Cadence Incisive version 11.10.017 to simulate a Stratix V design that includes a fractional phase-locked loop (PLL), and if a VHDL generic parameter and a local parameter have the same name regardless of case, NC-Sim might incorrectly match the two parameters.

For example, NC-Sim matches a generic parameter named pll_lock_fltr_test and a localparam named PLL_LOCL_FLTR_TEST.

Resolution

Upgrade to Incisive version 11.10.060 or later.