JESD204B IP Core Arria 10 Design Example Testbench - Simulation Failed During Reconfiguration

Description

When the reconfig port of the jesd204b_ed module is asserted during reconfiguration, the RX link error interrupt signal, jesd204_rx_int, is asserted because the rx_lockedtodata signal is deasserted. This is a correct behavior as transceiver is in reset state. However, the simulation testbench detects the interrupt signal and reports it as RX link error. When the simulation completes, the following message is shown:

# Pattern Checker(s): OK! # JESD204B Tx Core(s): OK! # JESD204B Rx Core(s): Rx link error(s) found! # Test passed count: Test passed count value 1 does not match predefined value 5! # TESTBENCH_FAILED: SIM FAILED!

Resolution

You need to manually clear the JESD204B IP core rx_err0 and rx_err1 status registers. Write a value of 0x0 to the registers upon reconfiguration done and before the link reset is deasserted.