JESD204B Arria 10 Design Example Simulation Failed in Soft PCS Mode

Description

When you generate the JESD204B design example from the IP catalog and enable soft PCS in the parameter editor, the testbench simulation fails and shows the following error message:

Running JESD204B Simulation: LINK=2, L=2, M=2, F=2, DATARATE/L=6.144Gbps

# Pattern Checker(s): No valid data found!

# JESD204B Tx Core(s): Tx link error(s) found!

# JESD204B Rx Core(s): OK!

# TESTBENCH_FAILED: SIM FAILED!

Resolution

Change the PMA_WIDTH setting of XCVR_ATX_PLL in the gen_ed_sim_verilog.tcl or gen_ed_sim_vhdl.tcl script from 20 to 40. Then run the script again to regenerate the correct simulation model.

This issue will be fixed in a future release.