Issues with multiple instantiations of RapidIO I IP core with different configurations in the Quartus Prime Pro Edition software

Description

When you instantiate different configurations of RapidIO I IP cores in your design, the library name collision across configurations will cause the synthesis engine to analyze incorrectly for those modules that share the same name across configurations. Your design may fail in synthesis due to the missing ports, or synthesize incorrectly that will cause abnormal behavior in hardware.

This issue affects the design in Quartus Prime Pro Edition software

Quartus Prime Standard Edition design is not impacted.

Resolution

Assign a unique library name for each of the .qip file generated with RapidIO IP core:

Step 1: Open <qsys_name>.qip in text editor.

Step 2: Replace each of the following default library name with a unique name.

• library "altera_rapidio_<acds_version>
• library "altera_xcvr_native_a10_<acds_version>"
• library "altera_xcvr_reset_control_<acds_version>"
• library "altera_xcvr_atx_pll_a10_<acds_version>"

For example:

set_global_assignment -library "altera_rapidio_160" -name SDC_FILE [file join $::quartus(qip_path)"altera_rapidio_160/synth/rio_altera_rapidio_160_puccaoq.sdc"]

set_global_assignment -library "altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/rio_altera_rapidio_160_puccaoq.v"]

set_global_assignment -library "altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/altera_rapidio_io_master.v"]

set_global_assignment -library "altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/altera_rapidio_io_slave.v"]

set_global_assignment -library "altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/alt_xcvr_resync.sv"]

set_global_assignment -library "altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/alt_xcvr_arbiter.sv"]

set_global_assignment -library "altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/twentynm_pcs.sv"]

set_global_assignment -library "altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/twentynm_pma.sv"]

Assign a unique name to each library:

set_global_assignment -library "<qsys_name>_altera_rapidio_160" -name SDC_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/rio_altera_rapidio_160_puccaoq.sdc"]

set_global_assignment -library "<qsys_name>_altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/rio_altera_rapidio_160_puccaoq.v"]

set_global_assignment -library "<qsys_name>_altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/altera_rapidio_io_master.v"]

set_global_assignment -library "<qsys_name>_altera_rapidio_160" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_rapidio_160/synth/altera_rapidio_io_slave.v"]

set_global_assignment -library "<qsys_name>_altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/alt_xcvr_resync.sv"]

set_global_assignment -library "<qsys_name>_altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/alt_xcvr_arbiter.sv"]

set_global_assignment -library "<qsys_name>_altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/twentynm_pcs.sv"]

set_global_assignment -library "<qsys_name>_altera_xcvr_native_a10_160" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_xcvr_native_a10_160/synth/twentynm_pma.sv"]

Step 3: Apply the steps above to other instances of RapidIO I IP core generated .qip files. Ensure that the library name given must be unique across .qip files.

Step 4: Compile your design. In the Spectra-Q Synthesis Source Files Read report, you will observe that RapidIO modules (altera_rapidio_*) are mapped to the library that you define in the .qip file.

This issue is fixed in 16.1 version of the RapidIO I IP core.