Is there a way to control the latency between afi_rdata_en and afi_rdata_valid in the UniPHY-based memory controllers?

Description

In UniPHY-based memory controllers, afi_rdata_en is asserted along with afi_cs_n to perform a read request. This read request is internally delayed in the PHY and used to capture the read data from the memory device. The PHY asserts afi_rdata_valid when it drives the valid read data on the afi_rdata bus. The latency between afi_rdata_en and afi_rdata_valid is not controllable because it is set during the calibration sequence in the PHY.

Resolution

This is an expected behavior, there is no plan to control the latency between afi_rdata_en and afi_rdata_valid in the UniPHY-based memory controllers.