Is there a known issue with Intel® Stratix® 10 FPGA 3V I/Os in user mode?

Description

Yes, due to a known problem in Intel® Quartus® Prime Pro Edition Software version 17.1 update 2 or earlier, when 3V I/Os in Intel® Stratix® 10 FPGAs are assigned to a static GND in the design, you might see an inversion at the output pin. 

3V I/Os are located in I/O banks 6A,6B,6C,7A,7B,7C, and are available in different density and package variants of Intel® Stratix® 10 devices.

Resolution

To work around this, use an input to drive the 3V I/O or place the signal assignment in a clocked process. 

This is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.