Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices?

Description

No, it is not possible to dynamically enable or disable Global Clock (GCLK) or Regional clock  (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices.

However, due to a problem in the Quartus® II software version 13.1 and earlier, if you use the enable signal on a clock control block that drives an fPLL, compilation will not fail.

Resolution

Future versions of the Quartus II software are scheduled to generate an error/warning message when  you use the enable signal on a clock control block that drives an fPLL,