IP Compiler for PCI Express Responds to User Write Request to Upper Dword With Incorrect Byte Enable

Description

When a Qsys-generated IP Compiler for PCI Express variation responds to an Avalon-MM write request to an upper dword address, the IP core generates a write transaction on the PCI Express link with the wrong byte enable. The expected dword address in the Memory Write Request TLP that the IP core generates and sends on the PCI Express link is 1 and the expected byte enable value is 0xF0. However, the IP core instead generates a TLP with dword address 0 and byte enable value 0x0F.

As a result of this error, the IP core writes the data to the lower dword, corrupting the user memory location at the remote endpoint.

Resolution

To fix this issue in the 11.1 SP1 software release, install the 11.1 SP1 Patch 1.16.

This issue is fixed in version 12.0 of the IP Compiler for PCI Express.