IP Compiler for PCI Express Qsys-Generated VHDL Testbench Cannot Simulate

Description

Qsys cannot generate a functional VHDL testbench for an IP Compiler for PCI Express.

This issue affects all IP Compiler for PCI Express variations generated in Qsys with a VHDL testbench.

Resolution

To avoid this issue, generate and simulate your design with the Verilog HDL testbench.

This issue will be fixed in a future version of the IP Compiler for PCI Express.