Internal Error: Sub-system: TILEIP, File: /quartus/db/tileip/tileip_writer.cpp, Line:3784

Description

The F-Tile Low Latency 50G Ethernet FPGA Soft-IP will fail to compile due to the use of a "vsr-mode=VSR_MODE_LOW_LOSS" constraint, causing a compilation error in the Quartus® Prime Pro Edition Software version 23.2.

Below are the error snapshots.

Resolution

To workaround this problem, change the alt_e50_f_hw.qsf  setting as vsr_mode=VSR_MODE_LOW_LOSS in the Quartus® Prime Pro Edition Software version 23.2.