Internal Error: Sub-system: REGPACK, File: /quartus/qcl/regpack/regpack_util.cpp, Line: 1190

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, you might see this internal error during the Plan stage of the Fitter. This problem can occur on the Arria® 10 and Cyclone® 10 DSP IPs since they do not have the input_systolic_clken or input_systolic_clock parameters.  

Resolution

To work around this problem, follow these steps in any order:

• Prevent output register packing by applying assignments on registers (1 is sufficient) or modify the RTL to move these registers to the input.
  • eg. set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to p_o[0]~reg0 -entity <name>
• Add synchronizer detection off assignments to all input registers.
  • eg. (* altera_attribute = {" -name SYNCHRONIZER_IDENTIFICATION OFF "} *) logic signed [DATA_WIDTH-1:0]   <input register>[1:0];

 

This problem is fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software.