Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 1073

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 Update 1 and earlier, you might see this internal error during compilation of an Intel® Stratix® 10 FPGA design when using the Signal lTap logic analyzer.

The internal error might occur when the Signal Tap logic analyzer file taps dedicated HPS nodes that are not accessible.

Resolution

To work around this problem, remove any dedicated HPS connections from the Signal Tap logic analyzer file.
The "Signal Tap: pre-synthesis" Filter or "Signal Tap: post-fitting" filter should be used when adding nodes to a Signal Tap logic analyzer file which will only return nodes that are accessible.