Internal Error: Sub-system: CIO, File: /quartus/periph/cio/cio_gen6.cpp, Line: 4625

Description

Due to a problem in the Quartus® Prime Pro Edition Software, you might see this internal error during the fitter stage of your compile. The error occurs when the tx_out_n output pins of the LVDS SERDES FPGA IP are left unconnected. This problem only affects designs targetting Agilex™ 7 M-Series FPGAs.

Resolution

To work around this problem, ensure the tx_out_n pins are connected to the complementary differential pin pair of the tx_out_p pins.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.