Internal Error: Sub-system: ASMPLL, File: /quartus/comp/asmpll/asmpll_28nm.cpp, Line: 231

Description

Due to a problem in the Quartus® II software version 12.0, you may see this error if your HDL code implements a PLL in normal or source-synchronous mode and drives an external clock output. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

Resolution

To work around this problem, do not use normal or source-synchronous mode and an external clock output at the same time.

The issue is fixed beginning with the Quartus II software version 12.0 SP1.