Intel® Stratix® 10 SerialLite III Streaming Design Example unable to compile due to fPLL error.

Description

When using the Intel® Stratix® 10 SerialLite III IP core Streaming design example, the following fPLL error may be seen depending on the transceiver reference clock frequency being used.

Error: altera_sl3_fpll.altera_sl3_fpll: Violating K limits for auto mode. The most common occurrence of this error is when refclk and output frequency combination can be synthesized in integer mode, and the user has selected fractional mode.

Resolution

To work around this issue, manually modify and regenerate the altera_sl3_fpll.ip file.

Using Qsys, open and edit the example design FPLL file located in:

\ed_synth\altera_sl3_fpll.ip

De-select the "Enable fractional mode" option, re-generate the IP, and re-compile.

This problem has been fixed in version 17.1 of the Intel® Quartus® Prime software.