Incorrect VHDL if Single Simulink Inport Block is Connected to Multiple ChannelIn Ports

Description

Connecting single Simulink Inport block to multiple ChannelIn ports may lead to VHDL error in synthesis.This issue affects primitive subsystems where a Simulink Inport block feeds into multiple ChannelIn portsWhen you compile for synthesis in the Quartus II software, you receive the following error, because the same port name appears multiple times in the port list:

Error (10465): VHDL error at one_inport_to_many_channelin_ports_Chip.vhd(40): name "d0" cannot be used because it is already used for a previously declared item

Resolution

Add a Simulink Inport block for each ChannelIn input in your subsystem, and feed the desired signals to those ports outside the subsystem.This issue will be fixed in a future release of the DSP Builder advanced blockset.