Incorrect Pin Mapping for DDR3 LRDIMM and LPDDR3 in Arria 10 EMIF

Description

This problem affects DDR3 LRDIMM and LPDDR3 interfaces on Arria 10 devices.

DDR3 LRDIMM

For DDR3 LRDIMM interfaces that employ the DDR3 Scheme 5: LRDIMM address/command pin mapping scheme, the IP incorrectly assigns pins to pin indexes within an I/O bank as follows:

Pin Index PAR_0 47 ALERT_N_0 46 CK_N_1 11 CK_1 10

The above pin-to-pin-index assignments are incorrect. The correct assignments are as follows:

Pin Index PAR_0 11 ALERT_N_0 10 CK_N_1 47 CK_1 46

LPDDR3

For LPDDR3 interfaces that employ the LPDDR3 Scheme 1 address/command pin mapping scheme, the IP incorrectly assigns pins to pin indexes within an I/O bank as follows:

Pin Index CK_N_3 34 CK_3 33 CK_N_2 32 CK_2 31

The above pin-to-pin-index assignment are incorrect. The correct assignments are as follows:

Pin Index CK_N_3 35 CK_3 34 CK_N_2 33 CK_2 32

Resolution

The workaround for this issue is to apply the correct pin assignments.

This issue is fixed in version 15.1.