Incorrect cmu_pll_inclock_period in Stratix II GX and Arria GX Designs

Description

For RapidIO variations that use the high-speed transceivers on a Stratix II GX or Arria GX device, the transceiver cmu_pll_inclock_period value is set incorrectly.

Simulation and compilation fail for the affected configurations.

Resolution

In the file <RapidIO instance name>_riophy_gxb.v, in the assignment to the alt2gxb_component.cmu_pll_inclock_period signal, assign the value 10⁶/<pll_inclk frequency> in place of the incorrect value.

To propagate the change to the IP functional simulation model, regenerate the model with the quartus_map command. Refer to the workaround for the erratum “The Demonstration Testbench May Fail for Some RapidIO Variations” for the appropriate command-line options.

This issue will be fixed in a future version of the RapidIO MegaCore function.