In ALTCLKCTRL MegaWizard, how does the register 'ena' port with 'Falling edge of input clock' affect the output signal?

Description

By using register \'ena\' port as \'Falling edge of input clock\', this will ensure the output clock always a complete clock pulse during enable/disable of register \'ena\'. Figure 1 shown the implementation of register \'ena\' in Altera device.

Figure 1.

In ALTCLKCTRL MegaWizard, if user select register \'ena\' port with \'Falling edge of input clock\', the output clock will be available one inclk falling edge after \'ena\' toggle high. Refer to Figure 2 for the functional diagram.

Figure 2.

The output clock will stop one inclk falling edge after \'ena\' toggle low. Refer to Figure 3 for the functional diagram.

Figure 3.