If my Verilog HDL design file has multiple cases listed on a single line of a Case Statement, only the first case appears to be implemented in the synthesized design. Why?

Description

The MAX PLUS^® II software does not support multiple cases written on one line of a Case Statement in Verilog HDL designs.

For example, the following code will only implement the first case, ignoring the second:

case(a)
  2'b00, 2'b11:  b <= 1;
  default:  b <= 0;
endcase

To avoid this problem, you should assign each case on a separate line:

case(a)
  2'b00: b <= 1;
  2'b11: b <= 1;
  default: b <= 0;
endcase

This problem was fixed in the MAX PLUS II software versions 9.2 and above.