How to handle the input port cfglink2csrpld of the SV PCIe HIP?

The port cfglink2csrpld is an undesired port in the HIP variation file. In the SV PCIe user guide there're no any descriptions regarding this signal.

You can connect the port cfglink2csrpld to "0" in your design. This port will be removed in Quartus II 12.0.

Updated 3 months ago

Version 3.0

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