How should I connect the clocks on the Triple-Speed Ethernet (TSE) MegaCore IP when implemented in Qsys

Description

When the TSE IP MAC is implemented in Qsys, the required clock connections are as detailed below:

Qsys Name :  Interface Description in the User Guide
control_port_clock_connection = clk (The MAC Control Interface Clock)
transmit_clock_connection = ff_tx_clk (The Avalon®-ST TX Clock)
receive_clock_connection = ff_rx_clk (The Avalon-ST RX Clock)

Exported from Qsys conduit name:
<TSE Qsys Component name>_pcs_mac_rx_clock_connection_clk : rx_clk ( PHY Interface RX Clock )
<TSE Qsys Component name>_pcs_mac_tx_clock_connection_clk : tx_clk ( PHY Interface TX Clock )