How many ALTGX_RECONFIG components should I use for a dynamic reconfiguration design that implements more than four PMA PCS channels clocked from a TX PLL outside of the transceiver bank, when using Stratix® IV GX devices?

Description

You should use one ALTGX_RECONFIG component for a dynamic reconfiguration design that implements more than four PMA PCS channels clocked from a TX PLL outside of the transceiver bank, when using Stratix IV GX devices.

Resolution

You can only connect one ALTGX_RECONFIG controller instance to a physical transceiver bank, but you can connect multiple transceiver banks to a single ALTGX_RECONFIG controller instance.

The example below shows an eight channel design configuration that uses two transceiver banks, and a CMU in each bank. Using dynamic reconfiguration and the XN clock network, all eight channels can be clocked from the CMU0 TX PLL from bank QL0 or the CMU0 TX PLL from bank QL1 and run independently at 2.5Gbps or 3.125Gbps.

IOBANK_QL1

GXB_[TX,RX]_CH7 = Channel 7

GXB_[TX,RX]_CH6 = Channel 6

GXB_CMU1 = Unused

GXB_CMU0 = Used as a TX PLL for 2.5Gbps

GXB_[TX,RX]_CH5 = Channel 5

GXB_[TX,RX]_CH4 = Channel 4

IOBANK_QL0

GXB_[TX,RX]_CH3 = Channel 3

GXB_[TX,RX]_CH2 = Channel 2

GXB_CMU1 = Unused

GXB_CMU0 = Used as a TX PLL for 3.125Gbps

GXB_[TX,RX]_CH1 = Channel 1

GXB_[TX,RX]_CH0 = Channel 0

Because each transceiver can be clocked from an alternate CMU that resides in the adjacent bank, and is shared amongst all eight channels, you must use one ALTGX_RECONFIG Controller IP component that connects to all ALTGX IP components