How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices?

Description

When you start a transceiver dynamic reconfiguration processes on Stratix® V and Arria® V transceiver devices, the Reconfiguration Controller "busy" signal will assert high within 3 "mgmt_clk_clk" cycles. You should wait until after the Reconfiguration Controller "busy" signal goes low again before starting the next process.

Updated 3 months ago

Version 2.0

arria® v fpgas and socs

stratix® v fpgas

troubleshooting

Knowledge Base Article

How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices?

Description